

#pragma  once



/***********************************************************************************************/
#define  BASE_AP_SRAM                   0x100000            /*512K*/
#define  BASE_AP_EXTRAM                 0x200000            /*8K*/
#define  BASE_AP_FLASH                  0x300000
#define  BASE_AP_TIMER0                 0x400000
#define  BASE_AP_TIMER1                 0x408000
#define  BASE_AP_TIMER2                 0x410000
#define  BASE_AP_TIMER3                 0x418000
#define  BASE_AP_TIMER4                 0x420000
#define  BASE_AP_TIMER5                 0x428000
#define  BASE_AP_PWM0                   0x430000
#define  BASE_AP_PWM1                   0x438000

#define  BASE_AP_CCP0                   0x440000
#define  BASE_AP_CCP1                   0x448000

#define  BASE_AP_SPI0                   0x460000            /* master */
#define  BASE_AP_SPI1                   0x468000            /* slave  */
#define  BASE_AP_SPI2                   0x470000            /* master */

#define  BASE_AP_GPIO0                  0x480000
#define  BASE_AP_GPIO1                  0x488000
#define  BASE_AP_GPIO2                  0x490000
#define  BASE_AP_GPIO3                  0x498000
#define  BASE_AP_GPIO4                  0x4A0000
#define  BASE_AP_GPIO5                  0x4A8000
#define  BASE_AP_GPIO6                  0x4B0000
#define  BASE_AP_GPIO7                  0x4B8000

#define  BASE_AP_DAC0                   0x4C0000
#define  BASE_AP_DAC1                   0x4C8000
#define  BASE_AP_ADC                    0x4D0000

#define  BASE_AP_INTC                   0x500000
#define  BASE_AP_WDT                    0x508000
#define  BASE_AP_RTC                    0x510000

#define  BASE_AP_UART0                  0x518000
#define  BASE_AP_UART1                  0x520000

#define  BASE_AP_I2C0                   0x530000
#define  BASE_AP_I2C1                   0x538000

#define  BASE_AP_SYSCTL                 0x540000
#define  BASE_AP_COMMREG                0x548000

#define  BASE_AP_PINMUX                 0x558000
#define  BASE_AP_FPGA                   0x560000
#define  BASE_AP_CAN                    0x580000

#define  BASE_AP_DMAC                   0x600000
#define  BASE_AP_ETHER                  0x610000
#define  BASE_AP_SUART0                 0x620000
#define  BASE_AP_SUART1                 0x628000
#define  BASE_AP_PDMA                   0x630000

#define  BASE_AP_DUALRAM                0x700000



/***********************************************************************************************/

#define  BASE_BB_DUALRAM                0x700000
#define  BASE_BB_SRAM                   0x800000
#define  BASE_BB_HCBMAC                 0xA00000

#define  BASE_BB_GPIO0                  0xC28000
#define  BASE_BB_GPIO1                  0xC30000

#define  BASE_BB_TIMER0                 0xC00000
#define  BASE_BB_TIMER1                 0xC08000
#define  BASE_BB_TIMER2                 0xC10000
#define  BASE_BB_TIMER3                 0xC18000

#define  BASE_BB_INTC                   0xC20000

#define  BASE_BB_GPIO0                  0xC28000
#define  BASE_BB_GPIO1                  0xC30000
#define  BASE_BB_COMMREG                0xC38000

#define  BASE_BB_CAN                    0xC40000
#define  BASE_BB_AFE                  	0xC68000


#define  BASE_BB_DMAC                   0xE00000
#define  BASE_BB_ETHER                  0xE10000
#define  BASE_BB_SUART                  0xE20000
#define  BASE_BB_PDMA                   0xE30000
#define  BASE_BB_HCBBUS                 0xE40000


/***********************************************************************************************/

/* LCR_DLAB == 0 */
#define  UARTC_RBR_OFFSET               0x00  /* receiver biffer register */
#define  UARTC_THR_OFFSET               0x00  /* transmitter holding register */
#define  UARTC_IER_OFFSET               0x04  /* interrupt enable register */
#define  UARTC_IIR_OFFSET               0x08  /* Read Only, interrupt identification register */
#define  UARTC_FCR_OFFSET               0x08  /* Write Only, FIFO control register */

/* LCR_DLAB == 1 */
#define  UARTC_DLL_OFFSET               0x00  /* baudrate divisor latch LSB */
#define  UARTC_DLH_OFFSET               0x04  /* baudrate divisor latch MSB */


/* LCR_DLAB == x */
#define  UARTC_LCR_OFFSET               0x0C  /* line control regitser */
#define  UARTC_MCR_OFFSET               0x10  /* modem control register */
#define  UARTC_LSR_OFFSET               0x14  /* line status register */
#define  UARTC_MSR_OFFSET               0x18  /* modem status register */
#define  UARTC_SCR_OFFSET               0x1c  /* scratch pad register */
#define  UARTC_TCR_OFFSET               0xAC  /* scratch pad register */
#define  UARTC_DEN_OFFSET				0xB0  /* Driver Output Enable */
#define  UARTC_REN_OFFSET				0xB4  /* Receiver Output Enable  */ 
#define  UARTC_DET_OFFSET				0xB8  /* Driver Output Enable Timing */
#define  UARTC_TAT_OFFSET				0xBC  /* TurnAround Timing */


/* LSR, Trans Empty flag*/
#define  SERIAL_LSR_THRE		            0x20
#define  SERIAL_LSR_DRDY		            0x01





/***********************************************************************************************/

#define  GPIOC_MODE             0x00
#define  GPIOC_DQ               0x04
#define  GPIOC_DQE              0x08
#define  GPIOC_DR               0x0C

#define  GPIOC_INT_POLA         0x10
#define  GPIOC_INT_TYPE         0x14
#define  GPIOC_INT_MASK         0x18
#define  GPIOC_INT_RAW          0x1C
#define  GPIOC_INT_STATUS       0x20
#define  GPIOC_INT_CLEAR        0x24

#define  GPIOC_DB_DIV           0x28
#define  GPIOC_DB_EN            0x2C


/***********************************************************************************************/

#define  TIMER_CLK_DIV          0x00
#define  TIMER_COMPARE          0x04
#define  TIMER_CURRENT          0x08
#define  TIMER_PWM              0x0C
#define  TIMER_ENABLE           0x10

#define  TIMER_INT_MASK         0x14
#define  TIMER_INT_RAW          0x18
#define  TIMER_INT_STATUS       0x1C
#define  TIMER_INT_CLR          0x20

#define  TIMER_MODE             0x24
#define  TIMER_CLEAR            0x28
#define  TIMER_RLD_VAL          0x2C
#define  TIMER_RELOAD           0x30


/***********************************************************************************************/

#define  COMMREG_INTRSET          0x00
#define  COMMREG_INTRCLR          0x04
#define  COMMREG_INTRMSK          0x08
#define  COMMREG_INTRRAW          0x0C
#define  COMMREG_INTRSTS          0x10

#define  COMMREG_APREG0           0x20
#define  COMMREG_APREG1           0x24
#define  COMMREG_APREG2           0x28
#define  COMMREG_APREG3           0x2C

#define  COMMREG_BBREG0           0x30
#define  COMMREG_BBREG1           0x34
#define  COMMREG_BBREG2           0x38
#define  COMMREG_BBREG3           0x3C


/***********************************************************************************************/

#define  INTC_ENABLE_L          0x00
#define  INTC_ENABLE_H          0x04
#define  INTC_MASK_L            0x08
#define  INTC_MASK_H            0x0C

#define  INTC_FORCE             0x10

#define  INTC_RAWS              0x18
#define  INTC_STATUS            0x20
#define  INTC_MASKS             0x28
#define  INTC_FINALS            0x30

#define  INTC_PRI_SYS           0xD8
#define  INTC_PRI_N(x)          (0xE8 + (x<<2))


/***********************************************************************************************/

#define  I2C_CON                  0x00
#define  I2C_TAR                  0x04
#define  I2C_SAR                  0x08
#define  I2C_HS_MADDR             0x0c
#define  I2C_DATA_CMD             0x10

#define  I2C_SS_SCL_HCNT          0x14
#define  I2C_SS_SCL_LCNT          0x18

#define  I2C_FS_SCL_HCNT          0x1c
#define  I2C_FS_SCL_LCNT          0x20

#define  I2C_INTR_STAT            0x2c
#define  I2C_INTR_MASK            0x30
#define  I2C_INTR_RAW             0x34

#define  I2C_RX_TL                0x38
#define  I2C_TX_TL                0x3c
#define  I2C_CLR_INTR             0x40

#define  I2C_ENABLE               0x6c
#define  I2C_STATUS               0x70

#define  I2C_TXFLR                0x74
#define  I2C_RXFLR                0x78

#define  I2C_TX_ABRT_SOURCE       0x80

#define  I2C_DMA_CR               0x88
#define  I2C_DMA_TDLR             0x8c
#define  I2C_DMA_RDLR             0x90

#define  I2C_TX_FIFO_SIZE         0x10
#define  I2C_RX_FIFO_SIZE         0x10



/***********************************************************************************************/

#define SF_FLASH_ID_REQ                 0x0
#define SF_FLASH_ID_VAL                 0x8
#define SF_FLASH_SCK                    0xc
#define SF_FLASH_INST_EXEC_TIMEOUT      0x20
#define SF_FLASH_EXEC_STATUS            0x24
#define SF_FLASH_USER_CMD               0x28
#define SF_FLASH_IRQ_STAT_RAW           0x2c   //write 1 clear
#define SF_FLASH_IRQ_MASK               0x30
#define SF_FLASH_IRQ_STAT               0x38
#define SF_FLASH_FIFO_WIDTH             0x34
#define SF_FLASH_FIFO_THRESHOLD         0x3c  //0:15 write threshold, 16:31 read threshold
#define SF_FLASH_FLR                    0x40             //0:15 read cnt,  16:31 write cnt
#define SF_FLASH_STATE_RESET            0x44
#define SF_FLASH_RXFIFO_RESET           0x48
#define SF_FLASH_TXFIFO_RESET           0x4c

//dma
#define SF_FLASH_DMA_EN                 0x5c
#define SF_FLASH_DMA_TX_WL              0x60
#define SF_FLASH_DMA_RX_WL              0x64

/**/
#define SF_RAMS_ADDR                    0x200
#define SF_REGS_ADDR                    0x300

/**/
#define SF_FLASH_FLR_WRITE_SHIFT    16
#define SF_FLASH_FIFO_WORD          0
#define SF_FLASH_FIFO_BYTE          1

/*irq*/
#define SF_IRQ_DONE                 0x2
#define SF_IRQ_TXFIFO_HALF_EMPTY    0x20
#define SF_IRQ_TXFIFO_EMPTY         0x40
#define SF_IRQ_RXFIFO_HALF          0x80
#define SF_IRQ_RXFIFO_FULL          0x100
#define SF_IRQ_TIMEOUT              0x200

#define SF_CMDS_MAX_WORDS       64
#define SF_REGS_MAX_WORDS       16



/***********************************************************************************************/

#define  MUX_CAN0_RX		0x000
#define  MUX_CAN0_TX		0x004

#define  MUX_UART0_TX		0x008
#define  MUX_UART0_RX		0x00C
#define  MUX_UART1_TX		0x010
#define  MUX_UART1_RX		0x014

#define  MUX_LD_EN_N		0x018

#define  MUX_SUART0_OCD		0x01C

#define  MUX_CCP1_PWM0_P	0x020
#define  MUX_CCP1_PWM0_N	0x024
#define  MUX_CCP1_PWM1_P	0x028
#define  MUX_CCP1_PWM1_N	0x02C
#define  MUX_CCP1_PWM2_P	0x030
#define  MUX_CCP1_PWM2_N	0x034
#define  MUX_CCP1_PWM3_P	0x038
#define  MUX_CCP1_PWM3_N	0x03C

#define  MUX_CCP0_PWM0_P	0x040
#define  MUX_CCP0_PWM0_N	0x044
#define  MUX_CCP0_PWM1_P	0x048
#define  MUX_CCP0_PWM1_N	0x04C
#define  MUX_CCP0_PWM2_P	0x050
#define  MUX_CCP0_PWM2_N	0x054
#define  MUX_CCP0_PWM3_P	0x058
#define  MUX_CCP0_PWM3_N	0x05C

#define  MUX_ETH1_RXD3		0x060
#define  MUX_ETH1_RXD2		0x064
#define  MUX_ETH1_RXD1		0x068
#define  MUX_ETH1_RXD0		0x06C
#define  MUX_ETH1_RXDV		0x070
#define  MUX_ETH1_RXCLK		0x074

#define  MUX_ETH1_TXD0		0x078
#define  MUX_ETH1_TXD1		0x07C
#define  MUX_ETH1_TXD2		0x080
#define  MUX_ETH1_TXD3		0x084
#define  MUX_ETH1_TXCLK		0x088

#define  MUX_ETH1_MDIO		0x08C
#define  MUX_ETH1_MDC		0x090
#define  MUX_ETH1_TXEN		0x094

#define  MUX_ETH0_RXD3		0x098
#define  MUX_ETH0_RXD2		0x09C
#define  MUX_ETH0_RXD1		0x0A0
#define  MUX_ETH0_RXD0		0x0A4
#define  MUX_ETH0_RXDV		0x0A8
#define  MUX_ETH0_RXCLK		0x0AC

#define  MUX_ETH0_TXD0		0x0B0
#define  MUX_ETH0_TXD1		0x0B4
#define  MUX_ETH0_TXD2		0x0B8
#define  MUX_ETH0_TXD3		0x0BC
#define  MUX_ETH0_TXCLK		0x0C0

#define  MUX_ETH0_MDIO		0x0C4
#define  MUX_ETH0_MDC		0x0C8
#define  MUX_ETH0_TXEN		0x0CC

/**/
#define  MUX_HCB_TXCLK		0x0D0
#define  MUX_HCB_TXSYNC		0x0D4

#define  MUX_SPI0_CLK		0x0D8
#define  MUX_SPI0_TX		0x0DC
#define  MUX_SPI0_RX		0x0E0

#define  MUX_SPI2_CLK		0x0E4
#define  MUX_SPI2_TX		0x0E8
#define  MUX_SPI2_RX		0x0EC

#define  MUX_SPI0_CS0		0x0F0
#define  MUX_SPI0_CS1		0x0F4
#define  MUX_SPI0_CS2		0x0F8
#define  MUX_SPI0_CS3		0x0FC

/**/
#define  MUX_SF_CLK			0x100
#define  MUX_SF_DI			0x104
#define  MUX_SF_CS			0x108
#define  MUX_SF_DO			0x10C
#define  MUX_SF_HOLD		0x110
#define  MUX_SF_WP			0x114


#define  MUX_I2C0_SDA		0x118
#define  MUX_I2C0_SCL		0x11C
#define  MUX_I2C1_SCL		0x120
#define  MUX_I2C1_SDA		0x124

/**/
#define  MUX_V_UP_PULL		0x04
#define  MUX_V_NO_PULL		0x00

#define  MUX_V_FUN0			0x00
#define  MUX_V_FUN1			0x01
#define  MUX_V_GPIO			0x02



